The present invention relates to sensor devices.
FIG. 1 shows an example of a prior art sensor array, formed at a surface of glass substrate 10. Gate 12 conventionally includes highly conductive metal and is connected to a scan line for receiving signals that control conductivity of a thin film transistor (TFT).
Insulating layer 20, conventionally silicon nitride (SiN), separates gate 12 from intrinsic semiconductor layer 22, the layer in which the TFT's channel is formed. Semiconductor layer 22 is conventionally amorphous silicon (a-Si), and it is covered in the channel region by insulating island 24, conventionally formed in another layer of SiN. The channel therefore extends from a connecting region at one side of island 24 to another connecting region at the other side of island 24.
Doped semiconductor layer 30 and conductive metal layer 32 are patterned to form channel leads for the TFT, and an opening is therefore formed over island 24 so that the channel leads are isolated. Doped semiconductor layer 30 includes one semiconductor lead in electrical contact with the connecting region at one side of island 24 and another semiconductor lead in electrical contact with the connecting region at the other side of island 24. For process compatibility, doped semiconductor layer 30 is conventionally heavily n-doped (n+) a-Si, while conductive metal layer 32 can be sputtered chromium.
Silicon-based sensor layer 40 is formed over metal layer 32 and acts as a diode. Sensor layer 40 can be formed in a conventional p-i-n layer or a Schottky diode layer, deposited in either case by plasma-enhanced chemical vapor deposition (PECVD), conventionally performed at temperatures greater than 180.degree. C., typically between 200-350.degree. C.
Over sensor layer 40, FIG. 1 also shows electrode layer 42, conventionally a layer of indium-tin-oxide (ITO), and lower passivation layer 44, conventionally a layer of silicon-based dielectric. Layer 44 is patterned to form openings to metal layer 32 on one side of the TFT and to ITO layer 42 on the other side. Then another conductive metal layer is deposited and patterned to provide data line 50 and bias line 52, connected respectively to metal layer 32 and ITO layer 42 through the openings. Finally upper passivation layer 46 covers the array, and is conventionally another layer of silicon-based dielectric.
Kanicki, J., Hasan, E., Griffith, J., Takamori, T., and Tsang, J. C., "Properties of High Conductivity Phosphorous Doped Hydrogenated Microcrystalline Silicon and Application in Thin Film Transistor Technology," Mat. Res. Soc. Symp. Proc., Vol. 149, 1989, pp. 239-246, describe techniques for phosphorous (P) doping of microcrystalline silicon (.mu.c-Si:H). At pages 239 and 245, Kanicki et al. describe use of a heavily (n+) P-doped .mu.c-Si:H layer in a hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a contact interlayer between a source/drain metal and a-Si:H layer. At page 239, Kanicki et al. mention application in sensing elements for integrated sensors. Beginning at page 240, Kanicki et al. describe preparation of n+ .mu.c-Si:H films by 13.56 MHz rf glow discharge decomposition of silane, phosphine, and hydrogen gas mixture, mentioning at page 241 that the hydrogen content decreases with increasing deposition temperatures, with higher temperature films containing less than 0.5 at. % of hydrogen, as shown in FIG. 3. At pages 245 and 246, Kanicki et al. describe bulk properties, contact properties, and application of an interlayer of .mu.c-Si:H between source/drain metal and a-Si:H in a TFT structure.
Lustig, N., and Kanicki, J., "Gate dielectric and contact effects in hydrogenated amorphous silicon-silicon nitride thin-film transistors," J. Appl. Phys., Vol. 65, May 1989, pp. 3951-3957, describe improvement in TFT mobility upon replacement of phosphorous doped (n+) hydrogenated amorphous silicon (a-Si:H) by n+ hydrogenated microcrystalline silicon (.mu.c-Si:H) in source-drain contact fabrication. Section II on pages 3951 and 3952 describes an experiment that included a thin n+ .mu.c-Si:H layer between source-drain metal and intrinsic a-Si:H, to insure ohmic contacts. The n+ .mu.c-Si:H was deposited from a PH.sub.3 /SiH.sub.4 mixture in H.sub.2 yielding an approximately 0.1-.OMEGA. cm material. The upper part of FIG. 1 shows a schematic cross section of a resulting transistor. As shown and described in relation to FIG. 5, average field-effect mobility increased with n+ .mu.c-Si:H.
Kawai et al., U.S. Pat. No. 5,473,168, describe a thin film transistor (TFT) used as a switching element for selectively switching a pixel electrode for an active matrix liquid crystal display. The TFT includes a substrate, a gate electrode on the substrate, a semiconductor layer insulated from the gate electrode, first and second contact layers of n-type microcrystalline silicon having a resistivity of 10 .OMEGA.cm or less, a source electrode in contact with part of the first contact layer, and a drain electrode in contact with part of the second contact layer. Various examples are shown and described in relation to figures 1-41. As described in relation to FIGS. 1 and 2, for example, phosphorous doped n+-type microcrystalline silicon (.mu.c-Si(n+)) is deposited by plasma CVD in an atmosphere of monosilane, phosphine, and hydrogen to a thickness of 50 nm.